1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a simultaneously-erasable non-volatile semiconductor memory device including memory cells each having a floating gate.
2. Description of Related Art
Recently, semiconductor memories have been developed to be highly integrated, highly densified and highly functionalized, and this development has enabled the semiconductor memories to compete with magnetic discs as memory material.
In a simultaneously (collectively) erasable non-volatile memory device, data erasing is performed by F-N (Fowler-Nordheim) tunnel current, and data writing is performed by hot-electron injection. This type semiconductor memory device has a disadvantage that data are excessively erased. However, a split-gate type non-volatile semiconductor device in which each memory cell has a split gate has an advantage that an excessive erasing state hardly occurs because a split portion serves as a select transistor.
FIG. 1 is a cross-sectional view showing the structure of a memory cell of a conventional split-gate type non-volatile semiconductor memory device which uses F-N tunnel current for erasing. In FIG. 1, reference numeral 201 represents a p-type silicon substrate, reference numeral 205 represents an n-type impurity diffusion layer which constitutes source and drain regions, reference numeral 208 represents a floating gate, reference numeral 213 represents a control gate which also serves as a split gate, reference numeral 207 represents a silicon oxide film which is a gate insulating film, reference numeral 212 represents a silicon oxide film which constitutes an interlayer film between the control gate 213 and the floating gate 208 and the gate insulating film of the split gate portion, and reference numeral 206 represents a silicon oxide film for insulating a buried diffusion layer (205) from the floating gate 208 and the control gate 213. The silicon oxide film 212 of the interlayer film between the control gate 213 and the floating gate 208 and the silicon oxide film 212 of the gate insulating film at the split portion are formed in the same process by a thermal oxidation treatment, and the thickness of the interlayer film between the control gate 213 and the floating gate 208 is set to be larger than that of the gate insulating film because the floating gate 208 exists.
In the conventional non-volatile memory device using F-N tunnel current for erasing as shown in FIG. 1, the data erasing is performed as follows. First, the control gate 213 and the substrate 201 are grounded, and a voltage of 12 V for example, is applied to the n-type impurity diffusion layer 205 at the right side of FIG. 1 which will be the drain region while the impurity region 205 at the left side which will be the source region is kept in an open state. At this time, electrons are discharged from the floating gate 208 to the drain region, and the threshold voltage of the transistor is reduced, so that the memory cell is kept in an data-erased state.
On the other hand, the data writing is performed as follows. A voltage of 12 V for example, is applied to the control gate 213, and 5 V to 8 V is applied to the drain region (n-type impurity diffusion layer 205 at the right side of FIG. 1) while the source region (n-type impurity diffusion layer 205 at the left side of FIG. 1) and the substrate 201 are grounded. At this time, current of about 0.5 to 1 mA flows in the channel region, and hot electrons are produced. Some of the hot electrons are doped into the floating gate 208 to increase the threshold voltage of the memory transistor, whereby the memory cell is kept in a write state.
In the memory transistor shown in FIG. 1, in order to reduce the applied voltages for the writing and erasing operations, the gate oxide film 207 under the floating gate 208 is required to be thinned. The thinning of the gate oxide film 207 enables the reduction of the drain voltage in the erasing operation and the gate voltage of the control gate 213 in the writing operation. In this case, an amount of current flowing into the memory transistor in the writing operation increases or it is unvaried.
This type of split-gate type non-volatile semiconductor memory device has been publicly known by Japanese Laid-open Patent Application No. Sho-62-271474, Japanese Laid-open Patent Application No. Hei-2-118997, etc. In addition, Japanese Laid-open Patent Application No. Sho-60-161673 discloses a semiconductor memory device having a different type memory cell, and it describes that both the erasing and writing operations are performed by tunnel current.
In the conventional split-gate type non-volatile semiconductor device as described above, the current consumption for the writing operation is large because the writing is performed by the hot electron injection. Furthermore, if the gate oxide film is thinned, the voltage to be applied to the control gate, etc. can be reduced, however, the current consumption is little varied. In addition, when large current is required, it is almost impossible to cover the current consumption with a booster circuit which is provided in an integration circuit. Therefore, it has been difficult for the conventional semiconductor memory device to achieve a single low-voltage power source of 5 V or less, for example, 3 V.
In view of the foregoing, it may be considered for reduction of the current consumption that the F-N tunnel current is enabled to be used for both the writing and erasing operations by applying the writing and erasing method as disclosed in Japanese Laid-open Patent Application No. Sho-60-161673 to the conventional non-volatile semiconductor memory device shown in FIG. 1. However, in this case, it is necessary to apply a high voltage to the control gate in the writing operation. At this time, the F-N tunnel current flows between the split gate (control gate) and the substrate because the thickness of the oxide film between the split gate and the substrate is not so large. Therefore, the oxide film on the split gate region is deteriorated, and the threshold voltage of the split gate region is varied by electrons injected into the oxide film, so that the operation of the memory transistor becomes unstable.
If the gate insulating film of the split gate portion is made thicker, the F-N tunnel current can be prevented from flowing between the control gate and the substrate. However, in the conventional memory cell as described above, the gate oxide film of the split gate portion and the oxide film between the floating gate and the control gate are formed in the same thermal oxidation process, so that the insulating film between the control gate and the floating gate is also made to have a large thickness. Therefore, controllability of the floating gate by the control gate is degraded, and thus an electron injection/discharge efficiency in the writing/erasing operation is also reduced. Alternatively, the voltage to be applied to the control gate in the writing and erasing operations must be further increased.